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21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74AVC+16345
2.5V, Registered 1-Bit to 4-Bit Address Driver w/3-State Outputs
Product Features
PI74AVC+16345 is designed for low-voltage operation, VCC = 1.65V to 3.6V True 24mA Balanced Drive @3.3V IOFF supports partial power down operation I/O Tolerant to 3.6V All outputs contain a patented DDC (Dynamic DriveControl) circuit that reduces noise without degrading propagation delay. Industrial operation: 40C to +85C Available Packages: 56-pin 240 mil wide plastic TSSOP (A) 56-pin 173 mil wide plastic TVSOP (K)
Product Description
Pericom Semiconductors PI74AVC+ series of logic circuits are produced using the Companys advanced submicron CMOS technology, achieving industry leading speed. The PI74AVC+16345 is ideal for driving memory modules in systems where multiple memory modules are used. One each of the four output banks drive a different module; modules can be added or removed without affecting the signal integrity of the other modules in the system. Dual clock enables (CEx) allow use of the device in high-speed memory interleaving applications where the clock can be alternately enabled and disabled, allowing the address to be held for additional cycles during memory access. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current sinking capability of the driver.
Logic Block Diagram
1 CE1 29 OE 1Q1 D1 8
CE D
56 CE2
1Q5 D5 36
CE D
4Q1
4Q5
1Q2 D2 14
CE D
1Q6 D6 42
CE D
4Q2
4Q6
1Q3 D3 15
CE D
1Q7 D7 43
CE D
4Q3
4Q7
1Q4 D4 21
CE D
1Q8 D8 49
CE D
4Q4 CLK 28
4Q8
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PS8442A
08/06/01
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74AVC+16345 2.5V, Registered 1-Bit to 4-Bit Address Driver with 3-State Outputs
Pin Description
Pin Name OE CLK CEX DX
XQX
Truth Table(1)
D e s cription 3- State O utput Enable Inputs (Active LO W) Clock Input Clock Enable Inputs (Active Low) Data Inputs 3- State O utputs Ground Power
Inputs CEx H X L L X OE L L L L H CLK X L X Dx X X L H X
Outputs xQx B0 B0 L H Z
GND VCC
Pin Configuration
CE1 1Q1 2Q1 GND 3Q1 4Q1 VCC D1 1Q2 2Q2 GND 3Q2 4Q2 D2 D3 1Q3 2Q3 GND 3Q3 4Q3 D4 VCC 1Q4 2Q4 GND 3Q4 4Q4 CLK 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 CE2 1Q8 2Q8 GND 3Q8 4Q8 VCC D8 1Q7 2Q7 GND 3Q7 4Q7 D7 D6 1Q6 2Q6 GND 3Q6 4Q6 D5 VCC 1Q5 2Q5 GND 3Q5 4Q5 OE
Note: 1. H = L= X= Z= = B0 =
High Signal Level Low Signal Level Irrelevant High Impedance LOW-to-HIGH Transition Previous State
56-Pin 44 A, K
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PS8442A
08/06/01
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74AVC+16345 2.5V, Registered 1-Bit to 4-Bit Address Driver with 3-State Outputs
Maximum Ratings
(Above which useful life may be impaired. For user guidelines, not tested.)
Supply voltage range, VCC .................................................... 0.5V to +4.6V Input voltage range, VI ............................................................ 0.5V to +4.6V Voltage range applied to any output in the high-impedance or power-off state, VO(1) .................... 0.5V to +4.6V Voltage range applied to any output in the high or low state, VO(1,2) ............................................... 0.5V to VCC +0.5V Input clamp current, IIK (VI <0) ............................................. 50mA Output clamp current, IOK (VO <0) ....................................... 50mA Continuous output current, IO ............................................................. 50mA Continuous current through each VCC or GND .................. 100mA Package thermal impedance, JA(3): package A .................... 64C/W package K .................... 48C/W Storage Temperature range, Tstg ....................................... 65C to 150C
Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. Notes: 1.Input & output negative-voltage ratings may be exceeded if the input and output curent rating are observed. 2.Output positive-voltage rating may be exceeded up to 4.6V maximum if theoutput current rating is observed. 3.The package thermal impedance is calculated in accordance with JESD 51.
Recommended Operating Conditions(1)
M in. VCC VIH Supply Voltage High- level Input Voltage Operating Data retention only VCC = 1.2V VCC = 1.65V to 1.95V VCC = 2.3V to 2.7V VCC = 3V to 3.6V VIL Low- level Input Voltage VCC = 1.2V VCC = 1.65V to 1.95V VCC = 2.3V to 2.7V VCC = 3V to 3.6V VI VO Input Voltage Output Voltage Active State 3- State IOH High- level output current VCC = 1.65V to 1.95V VCC = 2.3V to 2.7V VCC = 3V to 3.6V IOL Low- level output current VCC = 1.65V to 1.95V VCC = 2.3V to 2.7V VCC = 3V to 3.6V tv Input transition rise or fall rate TA Operating free- air temperature VCC = 1.65V to 3.6V 40 0 0 0 1.65 1.2 VCC 0.65 x VCC 1.7 2 Gnd 0.35 x VCC 0.7 0.8 3.6 VCC 3.6 6 12 24 6 12 24 5 85 ns/V C mA V M ax. 3.6 Units
Notes: 1. All unused inputs must be held at VCC or GND to ensure proper device operation.
3
PS8442A
08/06/01
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74AVC+16345 2.5V, Registered 1-Bit to 4-Bit Address Driver with 3-State Outputs
DC Electrical Characteristics (Over the Operating Range, TA = 40C +85C)
Parame te rs Te s t Conditions (1) IOH = 100A VOH IOH = 6mA IOH = 12mA IOH = 24mA IOL = 100A VOL IOL = 6mA IOL = 12mA IOL = 24mA II IOFF IOZ ICC Control Inputs CI Data Inputs CO Outputs VO = VCC or GND VI = VCC or GND Control Inputs VI = VCC or GND VI or VO = 3.6V VI = VCC or GND VO = VCC or GND IO = 0 VIH = 0.57V VIH = 0.7V VIH = 0.8V VIH = 1.07V VIH = 1.7V VIH = 2V VCC 1.65V to 3.6V 1.65V 2.3V 3V 1.65V to 3.6V 1.65V 2.3V 3V 3.6V 0 3.6V 3.6V 2.5V 3.3V 2.5V 3.3V 2.5V 3.3V 4 4 6 6 8 8 pF M in. VCC 0.2V 1.2 1.75 2.0 0.2 0.45 0.55 0.8 2.5 10 10 40 A V Typ. M ax. Units
Note: 1. Typical values are measured at TA = 25C.
4
PS8442A
08/06/01
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74AVC+16345 2.5V, Registered 1-Bit to 4-Bit Address Driver with 3-State Outputs
Timing Requirements
(Over recommended operating free-air temperature range, unless otherwise noted, see Figures 1 thru 4)
VCC = 1.2V M in fclock Clock Frequency tW Pulse Width, CLK High or Low M ax
VCC = 1.5V 0.1V M in M ax
VCC = 1.8V 0.15V M in 6.0 2.0 2.0 0 0.5 M ax 150
VCC = 2.5V 0.2V M in 3 1.5 1.5 0 0.5 M ax 180
VCC = 3.3V 0.3V M in M ax 180 3 1.5 1.5 0 0.5 ns Units MHz
tSU Setup Time, CEx to CLK , High or Low tSU Setup Time, Dx to CLK , High or Low tH tH Hold Time, CEx to CLK , High or Low Hold Time, CLK to Dx, High or Low
Switching Characteristics
(Over recommended operating free-air temperature range, unless otherwise noted, see Figures 1 thru 4)
Parame te rs fmax tpd ten tdis tSK(o) Output Skew(1) tSK(b) Output Skew(1)
From (Input) CLK OE OE
To (Output) xQx xQx xQx
VCC = 1.2V M in.
VCC = 1.5V 0.1V M ax.
VCC = 1.8V 0.15V M in. 150 4.5 5.3 5.6 0.5 0.3 M ax.
VCC = 2.5V 0.2V M in. 180 M ax. 3.1 4.5 3.6 0.5 0.3
VCC = 3.3V 0.3V M in. M ax. Units 180 2.7 3.9 3.4 0.5 0.3 ns
M ax. M in.
Note: 1. This is the skew between any two outputs of the same package, and switching in the same direction. For tSK(o) Output 1 and Output 2 are any two outputs. For tSK(b) Output 1 and Output 2 are in the same bank.
Operating Characteristics, TA= 25C
Parame te rs O utput Enabled O utputs Disabled Te s t Conditions VCC = 1.8V 0.15V Typical Cpd Power Dissipation Capacitance CL = 0pF, f = 10 MHZ Four outputs switching 84 48 VCC = 2.5V 0.2V Typical 95 55 VCC = 3.3V 0.3V Typical 110 63 pF Units
5
PS8442A
08/06/01
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74AVC+16345 2.5V, Registered 1-Bit to 4-Bit Address Driver with 3-State Outputs
PARAMETER MEASUREMENT INFORMATION VCC = 1.2V and 1.5V 0.1V
2xVCC From Output Under Test CL = 15pF
(See Note A)
2
S1
Open GND
Te s t tpd tPLZ/tPZL tPHZ/tPZH
S1 O pen 2 x VCC GND
2
Load Circuit
Timing Input tsu Data Input VCC VCC/2 0V th VCC VCC/2 VCC/2 0V
tW VCC Input VCC/2 VCC/2 0V
Voltage Waveforms Setup and Hold Times
Output Control (Low Level Enabling)
Voltage Waveforms Pulse Duration
VCC VCC/2 tPZL VCC/2 VOL +0.1V tPHZ VCC/2 VOH -0.1V VOH 0V VOL VCC/2 0V tPLZ VCC
VCC Input VCC/2 tPLH VCC /2 VCC/2 0V tPHL VOH Output VCC/2 VOL
Output Waveform 1 S1 at 2 x VCC (see Note B) t PZH Output Waveform 2 S1 at GND (see Note B)
Voltage Waveforms Propagation Delay Times
Voltage Waveforms Enable and Disable Times
Figure 1. Load Circuit and Voltage Waveforms
Notes: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input impulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50, tR 2.0ns, tF 2.0ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis F. tPZL and tPZH are the same as ten G. tPLH and tPHL are the same as tpd
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PS8442A
08/06/01
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PI74AVC+16345 2.5V, Registered 1-Bit to 4-Bit Address Driver with 3-State Outputs
PARAMETER MEASUREMENT INFORMATION VCC = 1.8V 0.15V
2xVCC From Output Under Test CL = 30 15pF
(See Note A)
1 k 2
S1
Open GND
Te s t tpd tPLZ/tPZL tPHZ/tPZH
S1 O pen 2 x VCC GND
2k 1
Load Circuit
Timing Input tsu Data Input VCC VCC/2 0V th VCC VCC/2 VCC/2 0V
tW VCC Input VCC/2 VCC/2 0V
Voltage Waveforms Setup and Hold Times
Output Control (Low Level Enabling)
Voltage Waveforms Pulse Duration
VCC VCC/2 tPZL VCC/2 VCC/2 0V tPLZ VCC VOL +0.1V 0.15V tPHZ VCC/2 VOH -0.1V 0.15V VOH 0V VOL
VCC Input VCC/2 tPLH VCC /2 VCC/2 0V tPHL VOH Output VCC/2 VOL
Output Waveform 1 S1 at 2 x VCC (see Note B) t PZH Output Waveform 2 S1 at GND (see Note B)
Voltage Waveforms Propagation Delay Times
Voltage Waveforms Enable and Disable Times
Figure 2. Load Circuit and Voltage Waveforms
Notes: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input impulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50, tR 2.0ns, tF 2.0ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis F. tPZL and tPZH are the same as ten G. tPLH and tPHL are the same as tpd
7
PS8442A
08/06/01
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74AVC+16345 2.5V, Registered 1-Bit to 4-Bit Address Driver with 3-State Outputs
PARAMETER MEASUREMENT INFORMATION VCC = 2.5V 0.2V
2xVCC From Output Under Test CL =30 15pF
(See Note A)
500 2 500 2
S1
Open GND
Te s t tpd tPLZ/tPZL tPHZ/tPZH
S1 O pen 2 x VCC GND
Load Circuit
Timing Input tsu Data Input VCC VCC/2 0V th VCC VCC/2 VCC/2 0V
tW VCC Input VCC/2 VCC/2 0V
Voltage Waveforms Setup and Hold Times
Output Control (Low Level Enabling)
Voltage Waveforms Pulse Duration
VCC VCC/2 tPZL VCC/2 VOL +0.15V tPHZ VCC/2 VOH -0.15V VOH 0V VOL VCC/2 0V tPLZ VCC
VCC Input VCC/2 tPLH VCC /2 VCC/2 0V tPHL VOH Output VCC/2 VOL
Output Waveform 1 S1 at 2 x VCC (see Note B) t PZH Output Waveform 2 S1 at GND (see Note B)
Voltage Waveforms Propagation Delay Times
Voltage Waveforms Enable and Disable Times
Figure 3. Load Circuit and Voltage Waveforms
Notes: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input impulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50, tR 2.0ns, tF 2.0ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis F. tPZL and tPZH are the same as ten G. tPLH and tPHL are the same as tpd
8
PS8442A
08/06/01
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74AVC+16345 2.5V, Registered 1-Bit to 4-Bit Address Driver with 3-State Outputs
PARAMETER MEASUREMENT INFORMATION VCC = 3.3V 0.3V
2xVCC From Output Under Test CL = 30 15pF
(See Note A)
500 2 500 2
S1
Open GND
Te s t tpd tPLZ/tPZL tPHZ/tPZH
S1 O pen 2 x VCC GND
Load Circuit
Timing Input tsu Data Input VCC VCC/2 0V th VCC VCC/2 VCC/2 0V
tW VCC Input VCC/2 VCC/2 0V
Voltage Waveforms Setup and Hold Times
Output Control (Low Level Enabling)
Voltage Waveforms Pulse Duration
VCC VCC/2 tPZL VCC/2 VCC/2 0V tPLZ VCC VOL +0.1V 0.3V tPHZ VCC/2 VOH -0.1V 0.3V VOH 0V VOL
VCC Input VCC/2 tPLH VCC /2 VCC/2 0V tPHL VOH Output VCC/2 VOL
Output Waveform 1 S1 at 2 x VCC (see Note B) t PZH Output Waveform 2 S1 at GND (see Note B)
Voltage Waveforms Propagation Delay Times
Voltage Waveforms Enable and Disable Times
Figure 4. Load Circuit and Voltage Waveforms
Notes: A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is high except when disabled by the output control. C. All input impulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50, tR 2.0ns, tF 2.0ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis F. tPZL and tPZH are the same as ten G. tPLH and tPHL are the same as tpd
9
PS8442A
08/06/01
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74AVC+16345 2.5V, Registered 1-Bit to 4-Bit Address Driver with 3-State Outputs
56-pin TSSOP (A) Package
56
.236 .244
6.0 6.2
1
.547 .555
13.9 14.1 1.20 .047 Max. SEATING PLANE
.004 0.09 .008 0.20 0.45 .018 0.75 .030 .319 BSC 8.1
.0197 BSC 0.50 X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS
.007 .011 0.17 0.27
.002 .006 0.05 0.15
56-pin TVSOP (K) Package
56
.169 .177
4.30 4.50
0.09 0.20 .0035 .008
1 .031 .041 0.80 1.05
0.45 .018 0.75 .030 .252 BSC 6.4 SEATING PLANE .047 1.20 Max.
.441 .449
11.20 11.40
.016 BSC 0.40 X.XX X.XX DENOTES DIMENSIONS IN MILLIMETERS
.005 .009 0.13 0.23
.002 .006 0.05 0.15
Ordering Information
Orde ring D ata PI74AVC+16345A PI74AVC+16345K D e s cription 56- pin, 240- mil wide plastic TSSO P 56- pin, 173- mil wide plastic TVSO P
Pericom Semiconductor Corporation 2380 Bering Drive * San Jose, CA 95131 * 1-800-435-2336 * Fax (408) 435-1100 * http://www.pericom.com
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PS8442A 08/06/01

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